The present invention relates to an output circuit and in particular to an output circuit that is suitable for suppressing overshoot or undershoot of its output waveform.
Liquid crystal display (LCD) drivers for driving an LCD include a voltage-follower-coupled operational amplifier as an output drive circuit. The transient characteristics of this operational amplifier are known to significantly affect display quality. In particular, overshoot or undershoot of its output waveform disadvantageously degrades image quality. Accordingly, an operational amplifier included in an LCD driver is required to suppress overshoot or undershoot of its output waveform.
However, the transconductance gm of an MOS transistor is generally lower than that of a bipolar transistor. For this reason, when an operational amplifier including an MOS analog drives a capacitive load, it disadvantageously tends to cause overshoot or undershoot in its drive waveform. Countermeasures to this problem include a method of increasing the W size of an output MOS transistor included in the operational amplifier to increase the transconductance gm. However, an increase in the W size of the output MOS transistor increases chip size, resulting in an increase in cost.
FIGS. 7A and 7B show equivalent circuits of an amplifier solely for positive voltages (hereafter referred to as a positive amplifier) 100 and an amplifier solely for negative voltages (hereafter referred to as a negative amplifier) 200 disclosed in Japanese Patent Application Publication No. 2009-194485. Specifically, FIGS. 7A and 7B show operational amplifiers for half_VDD which have been used in LCD drivers in recent years.
The positive amplifier 100 in FIG. 7A is an amplifier for driving voltages higher than a reference voltage COM (a reference voltage applied to the counter electrode of liquid crystal) in a liquid crystal display. The negative amplifier 200 shown in FIG. 7B is an amplifier for driving voltages lower than the reference voltage COM. As seen, in the field of liquid crystal displays, a voltage is determined to be positive or negative relative to the reference voltage COM. These positive and negative voltages are different from positive and negative voltages in general electrical engineering.
The positive amplifier 100 is an amplifier for driving the positive polarity of liquid crystal. Accordingly, if the reference voltage COM is a voltage halving the difference between a power supply voltage VDD and a ground voltage VSS, that is, VDD/2, the positive amplifier 100 is only required to drive voltages ranging from VDD/2 to VDD. On the other hand, the negative amplifier 200 is an amplifier for driving the negative polarity of the liquid crystal and therefore is only required to drive voltages ranging from VSS to VDD/2. Thus, in both amplifiers, the range of power supply voltages applied to an output stage circuit (output circuit) is about half that of power supply voltages applied to another circuit (here, differential stage circuit), thereby suppressing increases in power consumption.
The positive amplifier 100 shown in FIG. 7A includes a differential stage circuit 101 and an output stage circuit (output circuit) 102. The output stage circuit 102 includes a p-channel MOS transistor MP103 and an n-channel MOS transistor MN104. The output stage circuit 102 has a higher-potential power supply terminal to which the power supply voltage VDD is applied and a lower-potential power supply terminal to which an intermediate voltage VML is applied. The intermediate voltage VML is about half the power supply voltage VDD. The circuit (differential stage circuit 101) other than the output stage circuit 102 has a higher-potential power supply terminal to which the power supply voltage VDD is applied and a lower-potential power supply terminal to which the ground voltage VSS is applied.
The transistor MP103 has a source to which the power supply voltage VDD is applied, a drain coupled to an external output terminal Vout, and a gate coupled to one of output terminals of the differential stage circuit 101. The transistor MN104 has a source to which the intermediate voltage VML is applied, a drain coupled to the external output terminal Vout, and a gate coupled to the other output terminal of the differential stage circuit 101.
In the positive amplifier 100 shown in FIG. 7A, the differential stage circuit 101 outputs to the output stage circuit 102 a pair of amplified signals corresponding to the potential difference between input signals applied to input terminals IN+ and IN−. In the output stage circuit 102, a current flowing from the source of the transistor MP103 to the drain thereof is controlled on the basis of the amplified signal applied to the gate thereof. Similarly, a current flowing from the source of the transistor MN104 to the drain thereof is controlled on the basis of the amplified signal applied to the gate thereof. Since the power supply voltage VDD is applied to the source of the transistor MP103 and the intermediate voltage VML is applied to the source of the transistor MN104, the voltages of output signals of the positive amplifier 100 fall within the range of VDD/2 to VDD.
The negative amplifier 200 shown in FIG. 7B includes a differential stage circuit 201 and an output stage circuit (output circuit) 202. The output stage circuit 202 includes a p-channel MOS transistor MP203 and an n-channel MOS transistor MN204. The output stage circuit 202 has a higher-potential power supply terminal to which an intermediate voltage VMH is applied and a lower-potential power supply terminal to which the ground voltage VSS is applied. The intermediate voltage VMH is about half the power supply voltage VDD. The circuit (differential stage circuit 201) other than the output stage circuit 202 has a higher-potential power supply terminal to which the power supply voltage VDD is applied and a lower-potential power supply terminal to which the ground voltage VSS is applied.
The transistor MP203 has a source to which the intermediate voltage VMH is applied, a drain coupled to an external output terminal Vout, and a gate coupled to one of output terminals of the differential stage circuit 201. The transistor MN204 has a source to which the ground voltage VSS is applied, a drain coupled to the external output terminal Vout, and a gate coupled to the other output terminal of the differential stage circuit 201.
In the negative amplifier 200 shown in FIG. 7B, the differential stage circuit 201 outputs to the output stage circuit 202 a pair of amplified signals corresponding to the potential difference between input signals applied to input terminals IN+ and IN−. In the output stage circuit 202, a current flowing from the source of the output transistor MP203 to the drain thereof is controlled on the basis of the amplified signal applied to the gate thereof. A current flowing from the source of the transistor MN204 to the drain thereof is controlled on the basis of the amplified signal applied to the gate thereof. Since the intermediate voltage VMH is applied to the source of the transistor MP203 and the ground voltage VSS is applied to the source of the transistor MN204, the voltages of output signals of the negative amplifier 200 fall within the range of VSS to VDD/2.
Circuits for controlling a current to be supplied to a load include a circuit using a clamping circuit. FIG. 8 shows a circuit diagram of a transistor output circuit disclosed in Japanese Patent Application Publication No. Hei 3(1991)-117017. A transistor output circuit 300 shown in FIG. 8 includes a gate drive circuit 301, an output transistor 302, a clamping circuit 304, and a resistor 307 and controls a current flowing into a load 305 via the output transistor 302. As shown in FIG. 9, a current Id flowing from the source of the output transistor 302 to the drain thereof increases as the gate-source voltage Vgs thereof increases. That is, when the gate-source voltage Vgs of the output transistor 302 reaches or exceeds a predetermined voltage, an overcurrent is supplied to the load 305. For this reason, the transistor output circuit 300 includes the clamping circuit 304 between the gate and source of the output transistor 302. This prevents the gate-source voltage Vgs from reaching or exceeding the predetermined voltage, suppressing an overcurrent.
Japanese Patent No. 4228960 discloses a load drive apparatus including the same conductivity type of two MOS transistors coupled in series to a path for transmitting power from a power supply to a load; and clamping circuits coupled between the gates and drains of the two MOS transistors. Each clamping circuit includes a diode for backflow prevention and a clamp Zener diode (see FIG. 5 of the Patent).
Japanese Patent Application Publication No. Hei7(1995)-505994 discloses an inductive load damp circuit including an inductive load apparatus (L1), an n-channel MOS transistor (N1) coupled in series to the inductive load apparatus (L1), and a p-channel clamping transistor (P1) coupled between the gate and drain of the transistor (N1) (see FIG. 3 of the Publication). A power supply voltage Vcc is applied to the gate of the clamping transistor (P1).